View MAX1717_29565.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1636; Rev 0; 1/00
KIT ATION EVALU BLE AVAILA
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
General Description Features
o Quick-PWM Architecture o 1% VOUT Accuracy Over Line and Load o 5-Bit On-Board DAC with Input Mux o Precision-Adjustable VOUT Slew Control o 0.925V to 2V Output Adjust Range o Supports Voltage-Positioned Applications o 2V to 28V Battery Input Range o Requires a Separate +5V Bias Supply o 200/300/550/1000kHz Switching Frequency o Over/Undervoltage Protection o Drives Large Synchronous-Rectifier FETs o 700A typ ICC Supply Current o 2A typ Shutdown Supply Current o 2V 1% Reference Output o VGATE Transition-Complete Indicator o Small 24-Pin QSOP Package
MAX1717
The MAX1717 step-down controller is intended for core CPU DC-DC converters in notebook computers. It features a dynamically adjustable output, ultra-fast transient response, high DC accuracy, and high efficiency needed for leading-edge CPU core power supplies. Maxim's proprietary Quick-PWMTM quick-response, constant-on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns "instant-on" response to load transients while maintaining a relatively constant switching frequency. The output voltage can be dynamically adjusted through the 5-bit digital-to-analog converter (DAC) inputs over a 0.925V to 2V range. A unique feature of the MAX1717 is an internal multiplexer (mux) that accepts two 5-bit DAC settings with only five digital input pins. Output voltage transitions are accomplished with a proprietary precision slew-rate control that minimizes surge currents to and from the battery while guaranteeing "just-in-time" arrival at the new DAC setting. High DC precision is enhanced by a two-wire remotesensing scheme that compensates for voltage drops in the ground bus and output voltage rail. Alternatively, the remote-sensing inputs can be used together with the MAX1717's high DC accuracy to implement a voltage-positioned circuit that modifies the load-transient response to reduce output capacitor requirements and full-load power dissipation. Single-stage buck conversion allows these devices to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the +5V system supply instead of the battery) at a higher switching frequency allows the minimum possible physical size. The MAX1717 is available in a 24-pin QSOP package.
Ordering Information
PART MAX1717EEG TEMP. RANGE -40C to +85C PIN-PACKAGE 24 QSOP
Minimal Operating Circuit
+5V INPUT VCC
MAX1717
VDD V+ BST DH
BATTERY 2.5V TO 28V
Applications
Notebook Computers with SpeedStepTM or Other Dynamically Adjustable Processors 2-Cell to 4-Cell Li+ Battery to CPU Core Supply Converters 5V to CPU Core Supply Converters
Pin Configuration appears at end of data sheet.
Patent pending.
SKP/SDN FBS ILIM GNDS A/B REF TON CC D0 DAC INPUTS D1 D2 D3 D4
OUTPUT 0.925V TO 2V LX DL GND FB TIME VGATE
Quick-PWM is a trademark of Maxim Integrated Products. SpeedStep is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +30V VCC, VDD to GND .....................................................-0.3V to +6V D0-D4, A/B, VGATE, to GND ..................................-0.3V to +6V SKP/SDN to GND ...................................................-0.3V to +16V ILIM, FB, FBS, CC, REF, GNDS, TON, TIME to GND .................................-0.3V to (VCC + 0.3V) DL to GND ..................................................-0.3V to (VDD + 0.3V) BST to GND ............................................................-0.3V to +36V DH to LX .....................................................-0.3V to (BST + 0.3V) LX to BST..................................................................-6V to +0.3V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation 24-Pin QSOP (derate 9.5mW/C above +70C)...........762mW Operating Temperature Range ..........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = SKP/SDN = +5V, VOUT = 1.6V, TA = 0C to +85C, unless otherwise noted.) PARAMETER PWM CONTROLLER Input Voltage Range DC Output Voltage Accuracy (Note 1) Remote Sense Voltage Error Line Regulation Error FB Input Resistance FBS Input Bias Current GNDS Input Bias Current TIME Frequency Accuracy Battery voltage, V+ VCC, VDD V+ = 4.5V to 28V, includes load regulation error DAC codes from 1.3V to 2V DAC codes from 0.925V to 1.275V 2 4.5 -1 -1.2 3 5 180 28 5.5 1 1.2 V % % mV mV k A A % CONDITIONS MIN TYP MAX UNITS
FB to FBS or GNDS to GND = 0 to 25mV VCC = 4.5V to 5.5V, VBATT = 4.5V to 28V 115 -0.2 -1 150kHz nominal, RTIME = 120k 380kHz nominal, RTIME = 47k 38kHz nominal, RTIME = 470k V+ = 5V, FB = 2V, TON = GND (1000kHz) TON = REF (550kHz) V+ = 24V, FB = 2V TON = open (300kHz) TON = VCC (200kHz) -8 -12 -12 375 135 260 375
265 0.2 1 +8 +12 +12
425 155 289 418 400 300 700 <1 25
475 173 318 461 500 375 1200 5 40 5 5 5 2.02 ns ns A A A A A A V ns
On-Time (Note 2)
Minimum Off-Time (Note 2) Minimum Off-Time (Note 2) BIAS AND REFERENCE Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Battery Supply Current (V+) Reference Voltage 2
TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) TON = GND (1000kHz) Measured at VCC, FB forced above the regulation point Measured at VDD, FB forced above the regulation point
SKP/SDN = 0 SKP/SDN = 0 SKP/SDN = 0, VCC = VDD = 0 or 5V VCC = 4.5V to 5.5V, no REF load 1.98
2 <1 <1 2
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = SKP/SDN = +5V, VOUT = 1.6V, TA = 0C to +85C, unless otherwise noted.) PARAMETER Reference Load Regulation REF Sink Current FAULT PROTECTION Overvoltage Trip Threshold Overvoltage Fault Propagation Delay Output Undervoltage Fault Protection Threshold Output Undervoltage Fault Propagation Delay Output Undervoltage Fault Blanking Time Current-Limit Threshold (Positive, Default) Current-Limit Threshold (Positive, Adjustable) Current-Limit Threshold (Negative) Current-Limit Threshold (Zero Crossing) Current-Limit Default Switchover Threshold Thermal Shutdown Threshold VCC Undervoltage Lockout Threshold VGATE Lower Trip Threshold VGATE Upper Trip Threshold VGATE Propagation Delay VGATE Transition Delay VGATE Output Low Voltage VGATE Leakage Current GATE DRIVERS DH Gate Driver On-Resistance DL Gate Driver On-Resistance DH Gate-Driver Source/Sink Current DL Gate-Driver Sink Current BST - LX forced to 5V DL, high state (pull up) DL, low state (pull down) DH forced to 2.5V, BST - LX forced to 5V DL forced to 2.5V 1.0 1.0 0.4 1.3 4 3.5 3.5 1.0 A A 3 Hysteresis = 10C Rising edge, hysteresis = 20mV, PWM disabled below this level Measured at FB with respect to unloaded output voltage, rising edge, hysteresis = 1% Measured at FB with respect to unloaded output voltage, rising edge, hysteresis = 1% FB forced 2% outside VGATE trip threshold After X = Y, clock speed set by RTIME ISINK = 1mA High state, forced to 5.5V 4.1 -8 +10 -6.5 +12 1.5 1 0.4 1 Measured at FB FB forced 2% above trip threshold With respect to unloaded output voltage FB forced 2% below trip threshold From SKP/SDN signal going high, clock speed set by RTIME GND - LX, ILIM = VCC GND - LX LX - GND, ILIM = VCC GND - LX 3 TA = +25C to +85C TA = 0C to +85C ILIM = 0.5V ILIM = REF (2V) 90 85 35 165 -140 50 200 -110 4 VCC - 1 VCC - 0.4 150 4.4 -5 +14 65 2.20 2.25 1.5 70 10 256 100 110 115 65 230 -80 75 2.30 V s % s clks mV mV mV mV V C V % % ms clk V A IREF = 0 to 50A REF in regulation 10 CONDITIONS MIN TYP MAX 0.01 UNITS V A
MAX1717
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = SKP/SDN = +5V, VOUT = 1.6V, TA = 0C to +85C, unless otherwise noted.) PARAMETER DL Gate-Driver Source Current Dead Time LOGIC AND I/O Logic Input High Voltage Logic Input Low Voltage DAC B-Mode Programming Resistor, Low DAC B-Mode Programming Resistor, High D0-D4 Pull Up/Down Logic Input Current D0-D4, A/B D0-D4, A/B D0-D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, A/B = GND D0-D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, A/B = GND Entering B mode D0-D4, A/B = 5V A/B For TON = VCC (200kHz operation) TON Input Levels For TON = open (300kHz operation) For TON = REF (550kHz operation) For TON = GND (1000kHz operation) SKP/SDN and TON Input Current SKP/SDN, TON forced to GND or VCC SKP/SDN = logic high (SKIP mode) SKP/SDN = open (PWM mode) SKP/SDN = logic low (shutdown mode) To enable no-fault mode -3 2.8 1.8 12 Pull up Pull down -1 -1 VCC - 0.4 3.15 1.65 3.85 2.35 0.5 3 6 2.2 0.5 15 A V 95 40 8 1 1 1.05 k k A 2.4 DL forced to 2.5V DL rising DH rising CONDITIONS MIN TYP 1.3 35 26 MAX UNITS A ns
SKP/SDN Input Levels
V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = SKP/SDN = +5V, VOUT = 1.6V, TA = -40C to +85C, unless otherwise noted.) (Note 3) PARAMETER DC Output Voltage Accuracy (Note 1) V+ = 4.5V to 28V, includes load regulation error CONDITIONS DAC codes from 1.3V to 2V DAC codes from 0.925V to 1.275V MIN -1.5 -1.7 -8 -12 -12 375 136 260 365 TYP MAX 1.5 % 1.7 +8 +12 +12 475 173 318 471 500 375 ns ns ns ns % UNITS
150kHz nominal, RTIME = 120k TIME Frequency Accuracy On-Time (Note 2) On-Time (Note 2) Minimum Off-Time (Note 2) Minimum Off-Time (Note 2) 4 380kHz nominal, RTIME = 47k 38kHz nominal, RTIME = 470k V+ = 5V, FB = 2V, TON = GND (1000kHz) TON = REF (550kHz) V+ = 24V, FB = 2V TON = open (300kHz) TON = VCC (200kHz) TON = VCC, open, or REF (200kHz, 300kHz, or 550kHz) TON = GND (1000kHz)
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = SKP/SDN = +5V, VOUT =1.6V, TA = -40C to +85C, unless otherwise noted.) (Note 3) PARAMETER Quiescent Supply Current (VCC) Quiescent Supply Current (VDD) Quiescent Battery Supply Current (V+) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) Shutdown Battery Supply Current (V+) Reference Voltage Overvoltage Trip Threshold Output Undervoltage Protection Threshold Current-Limit Threshold (Positive, Default) Current-Limit Threshold (Positive, Adjustable) Current-Limit Threshold (Negative) VCC Undervoltage Lockout Threshold DH Gate Driver On-Resistance DL Gate Driver On-Resistance Logic Input High Voltage Logic Input Low Voltage DAC B-Mode Programming Resistor, Low DAC B-Mode Programming Resistor, High VGATE Lower Trip Threshold VGATE Upper Trip Threshold SKP/SDN = 0 SKP/SDN = 0 SKP/SDN = 0, VCC = VDD = 0 or 5V VCC = 4.5V to 5.5V, no REF load Measured at FB With respect to unloaded output voltage GND - LX, ILIM = VCC GND - LX LX - GND, ILIM = VCC Rising edge, hysteresis = 20mV, PWM disabled below this level BST - LX forced to 5V DL, high state (pull up) DL, low state (pull down) D0-D4, A/B D0-D4, A/B D0-D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, A/B = GND D0-D4, 0 to 0.4V or 2.6V to 5.5V applied through resistor, A/B = GND Measured at FB with respect to unloaded output voltage, falling edge, hysteresis = 1% Measured at FB with respect to unloaded output voltage, rising edge, hysteresis = 1% 100 -8.4 +10 -4.6 +15 2.4 0.8 1 ILIM = 0.5V ILIM = REF (2V) 1.98 2.20 65 80 33 160 -140 4.1 CONDITIONS Measured at VCC, FB forced above the regulation point Measured at VDD, FB forced above the regulation point MIN TYP MAX 1200 5 40 5 5 5 2.02 2.30 75 115 65 240 -80 4.4 3.5 3.5 1.0 UNITS A A A A A A V V % mV mV mV V V V k k % %
MAX1717
Note 1: Output voltage accuracy specifications apply to DAC voltages from 0.925V to 2V. Includes load-regulation error. Note 2: On-Time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds. Note 3: Specifications to -40C are guaranteed by design and not production tested.
_______________________________________________________________________________________
5
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Typical Operating Characteristics
(Circuit of Figure 1, components of Table 1, V+ = +12V, VDD = VCC = SKP/SDN = +5V, VOUT = 1.6V, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT 300kHz STANDARD APPLICATION, CIRCUIT 1
MAX1717 toc01
EFFICIENCY vs. LOAD CURRENT 300kHz VOLTAGE POSITIONED, CIRCUIT 2
MAX1717 toc02
EFFECTIVE EFFICIENCY vs. LOAD CURRENT 300kHz VOLTAGE POSITIONED, CIRCUIT 2
SKIP MODE, V+ = 7V EFFECTIVE EFFICIENCY (%) 90 SKIP MODE, V+ = 12V SKIP MODE, V+ = 20V PWM MODE, V+ = 7V
MAX1717 toc03
100 SKIP MODE, V+ = 7V 90 EFFICIENCY (%) SKIP MODE, V+ = 12V SKIP MODE, V+ = 20V PWM MODE, V+ = 7V
100 SKIP MODE, V+ = 7V 90 EFFICIENCY (%) SKIP MODE, V+ = 12V SKIP MODE, V+ = 20V PWM MODE, V+ = 7V PWM MODE, V+ = 12V 60 PWM MODE, V+ = 20V 50 0.01 0.1 1 10
100
80
80
80
70 PWM MODE, V+ = 12V 60 PWM MODE, V+ = 20V 50 0.01 0.1 1 10 LOAD CURRENT (A)
70
70 PWM MODE, V+ = 12V PWM MODE, V+ = 20V 50 0.01 0.1 1 10
60
LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT 550kHz VOLTAGE POSITIONED, CIRCUIT 3
MAX1717 toc04
EFFECTIVE EFFICIENCY vs. LOAD CURRENT 550kHz VOLTAGE POSITIONED, CIRCUIT 3
MAX1717 toc05
EFFICIENCY vs. LOAD CURRENT 1000kHz, +5V, CIRCUIT 4
SKIP MODE 90 EFFICIENCY (%)
MAX1717 toc06
100 SKIP MODE, V+ = 7V 90 EFFICIENCY (%) SKIP MODE, V+ = 12V PWM MODE, V+ = 7V SKIP MODE, V+ = 20V 70 PWM MODE, V+ = 12V PWM MODE, V+ = 20V 0.01 0.1 1 10
100 SKIP MODE, V+ = 7V EFFECTIVE EFFICIENCY (%) 90 SKIP MODE, V+ = 12V PWM MODE, V+ = 7V SKIP MODE, V+ = 20V 70 PWM MODE, V+ = 12V PWM MODE, V+ = 20V 0.01 0.1 1 10
100
80
80
80 PWM MODE
70
60
60
60
50
50
50 0.01 0.1 1 10 LOAD CURRENT (A)
LOAD CURRENT (A)
NONPOSITIONED LOAD CURRENT (A)
EFFECTIVE EFFICIENCY vs. LOAD CURRENT 1000kHz, +5V, CIRCUIT 4
MAX1717 toc07
EFFICIENCY vs. LOAD CURRENT 1000kHz VOLTAGE POSITIONED, CIRCUIT 5
MAX1717 toc08
EFFECTIVE EFFICIENCY vs. LOAD CURRENT 1000kHz VOLTAGE POSITIONED, CIRCUIT 5
SKIP MODE, V+ = 7V EFFECTIVE EFFICIENCY (%) 90 SKIP MODE, V+ = 12V PWM MODE, V+ = 7V SKIP MODE, V+ = 20V PWM MODE, V+ = 12V PWM MODE, V+ = 20V 0.01 0.1 1 10
MAX1717 toc09
100 SKIP MODE EFFECTIVE EFFICIENCY (%) 90
100 SKIP MODE, V+ = 7V 90 EFFICIENCY (%) SKIP MODE, V+ = 12V PWM MODE, V+ = 7V SKIP MODE, V+ = 20V PWM MODE, V+ = 12V PWM MODE, V+ = 20V 50
100
80 PWM MODE
80
80
70
70
70
60
60
60
50 0.01 0.1 1 10 NONPOSITIONED LOAD CURRENT (A)
50 0.01 0.1 1 10 LOAD CURRENT (A) NONPOSITIONED LOAD CURRENT (A)
6
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, VDD = VCC = SKP/SDN = +5V, VOUT = 1.6V, TA = +25C, unless otherwise noted.)
FREQUENCY vs. LOAD CURRENT
MAX1717 toc10
MAX1717
FREQUENCY vs. LOAD CURRENT
MAX1717 toc11
FREQUENCY vs. INPUT VOLTAGE
300kHz VOLTAGE POSITIONED, CIRCUIT 2
MAX1717 toc12
400
300kHz VOLTAGE POSITIONED, CIRCUIT 2 PWM MODE
1250 1000 FREQUENCY (kHz)
1000kHz VOLTAGE POSITIONED, CIRCUIT 5 PWM MODE
400
300 FREQUENCY (kHz)
350 FREQUENCY (kHz) IOUT = 12A 300
750
200 SKIP MODE 100
500
SKIP MODE
250
250
IOUT = 0.3A
0 0 3 6 LOAD CURRENT (A) 9 12
0 0 3 6 LOAD CURRENT (A) 9 12
200 5 10 15 INPUT VOLTAGE (V) 20 25
FREQUENCY vs. INPUT VOLTAGE
MAX1717 toc13
FREQUENCY vs. TEMPERATURE
MAX1717 toc14
OUTPUT CURRENT AT CURRENT LIMIT vs. TEMPERATURE
300kHz VOLTAGE POSITIONED, CIRCUIT 2
MAX1717 toc15
1200
1000kHz VOLTAGE POSITIONED, CIRCUIT 5
350
300kHz VOLTAGE POSITIONED, CIRCUIT 2
30 25 20 15 10
1000 FREQUENCY (kHz) IOUT = 12A 800 FREQUENCY (kHz)
340
330
320
600
IOUT = 0.3A
310
CURRENT (A) -40 -20 0 20 40 60 80 85
5 0 -40 -20 0 20 40 60 80 85 TEMPERATURE (C) TEMPERATURE (C)
400 5 10 15 INPUT VOLTAGE (V) 20 25
300
CONTINUOUS-TO-DISCONTINUOUS INDUCTOR CURRENT POINT
MAX1717 toc16
INDUCTOR CURRENT PEAKS AND VALLEYS vs. INPUT VOLTAGE
MAX1717 toc17
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
300kHz VOLTAGE POSITIONED, CIRCUIT 2, SKIP MODE ICC + IDD 600
MAX1717 toc18
3.0 2.5 LOAD CURRENT (A) 2.0 1.5 1.0 0.5 0 0
300kHz VOLTAGE POSITIONED, CIRCUIT 2
30 25 INDUCTOR CURRENT (A) 20 15 10 5 0 AT CURRENT-LIMIT POINT 300kHz VOLTAGE POSITIONED, CIRCUIT 2 5 7 9 IPEAK IVALLEY
1000 800 SUPPLY CURRENT (A)
400
200 I+ 5 10 15 INPUT VOLTAGE (V) 20 25
0
5
10
15
20
25
11 13 15 17 19 21 23 25 INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, VDD = VCC = SKP/SDN = +5V, VOUT = 1.6V, TA = +25C, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1717 toc19
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1717 toc20
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1717 toc21
1000 800 SUPPLY CURRENT (A)
1000kHz VOLTAGE POSITIONED, CIRCUIT 5, SKIP MODE ICC + IDD
40
40
600
SUPPLY CURRENT (mA)
30
SUPPLY CURRENT (mA)
30 ICC + IDD 20 I+ 10
20 ICC + IDD I+ 10
400
200 I+ 0 5 10 15 INPUT VOLTAGE (V) 20 25
0 5
300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE 10 15 INPUT VOLTAGE (V) 20 25
0 5
550kHz VOLTAGE POSITIONED, CIRCUIT 3, PWM MODE 10 15 INPUT VOLTAGE (V) 20 25
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX1717 toc22
LOAD-TRANSIENT RESPONSE
MAX1717 toc23
LOAD-TRANSIENT RESPONSE
300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE
MAX1717 toc24 MAX1717 toc27
40
300kHz STANDARD APPLICATION, CIRCUIT 1, PWM MODE
SUPPLY CURRENT (mA)
30 ICC + IDD I+ 20 A A
10 1000kHz VOLTAGE POSITIONED, CIRCUIT 5, PWM MODE 0 5 10 15 INPUT VOLTAGE (V) 20 25 10s/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div 10s/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div B B
LOAD-TRANSIENT RESPONSE
550kHz VOLTAGE POSITIONED, CIRCUIT 3, PWM MODE
MAX1717 toc25
LOAD-TRANSIENT RESPONSE
1000kHz +5V, CIRCUIT 4, PWM MODE
MAX1717 toc26
LOAD-TRANSIENT RESPONSE
1000kHz VOLTAGE POSITIONED, CIRCUIT 5, PWM MODE
A
A
A
B 5s/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div
B
B 4s/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div 4s/div A = VOUT, 50mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div
8
_______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, VDD = VCC = SKP/SDN = +5V, VOUT = 1.6V, TA = +25C, unless otherwise noted.)
STARTUP WAVEFORM
MAX1717 toc28
MAX1717
STARTUP WAVEFORM
MAX1717 toc29
DYNAMIC OUTPUT VOLTAGE TRANSITION
A
MAX1717 toc30
300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE, NO LOAD A
300kHz VOLTAGE POSITIONED, CIRCUIT 2, IOUT =12A A
B
B
B
C 100s/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div
C 100s/div A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div
C D 50s/div 300kHz STANDARD APPLICATION, CIRCUIT 1, PWM MODE, VOUT = 1.35V TO 1.6V, IOUT = 0.3A, RTIME = 120k A = VOUT, 200mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = A/B, 5V/div
DYNAMIC OUTPUT VOLTAGE TRANSITION
MAX1717 toc31
DYNAMIC OUTPUT VOLTAGE TRANSITION
MAX1717 toc32
OUTPUT OVERLOAD WAVEFORM
300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE
MAX1717 toc33
A
A
B
B
A
C D 50s/div 300kHz STANDARD APPLICATION, CIRCUIT 1, PWM MODE, VOUT = 1.35V TO 1.6V, IOUT = 12A, RTIME = 120k A = VOUT, 200mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = A/B, 5V/div
C D 20s/div A = VOUT, 200mV/div, AC-COUPLED B = INDUCTOR CURRENT, 10A/div C = VGATE, 5V/div D = A/B, 5V/div 1000kHz +5V, CIRCUIT 4, PWM MODE, VOUT = 1.35V TO 1.6V, IOUT = 0.3A, RTIME = 51k
B 40s/div A = VOUT, 500mV/div B = INDUCTOR CURRENT, 10A/div
_______________________________________________________________________________________
9
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Typical Operating Characteristics (continued)
(Circuit of Figure 1, components of Table 1, V+ = +12V, VDD = VCC = SKP/SDN = +5V, VOUT = 1.6V, TA = +25C, unless otherwise noted.)
SHUTDOWN WAVEFORM
MAX1717 toc34
SHUTDOWN WAVEFORM
MAX1717 toc35
A
A
B
B
C
C
100s/div 300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE, NO LOAD A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div
100s/div 300kHz VOLTAGE POSITIONED, CIRCUIT 2, PWM MODE, IOUT = 12A A = VOUT, 1V/div B = INDUCTOR CURRENT, 10A/div C = SKP/SDN, 5V/div
Pin Description
PIN 1 NAME V+ FUNCTION Battery Voltage Sense Connection. Connect V+ to input power source. V+ is used only for PWM one-shot timing. DH on-time is inversely proportional to input voltage over a range of 2V to 28V. Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown. Leave SKP/SDN open for low-noise forced-PWM mode, or drive to VCC for normal pulse-skipping operation. Low-noise forced-PWM mode causes inductor current recirculation at light loads and suppresses pulse-skipping operation. SKP/SDN can also be used to disable over/undervoltage protection circuits and clear the fault latch by forcing it to 12V < SKP/SDN < 15V (with otherwise normal PFM/PWM operation). Do not connect SKP/SDN to > 15V. Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 470k to 47k resistor sets the clock from 38kHz to 380kHz, SLEW = 150kHz * 120k / RTIME. Fast Feedback Input. Connect FB to the junction of the external inductor and output capacitor for nonvoltage-positioned circuits (Figure 1). For voltage-positioned circuits, connect FB to the junction of the external inductor and the positioning resistor (Figure 3). Feedback Remote-Sense Input. For nonvoltage-positioned circuits, connect FBS to VOUT directly at the load. FBS internally connects to the integrator that fine tunes the DC output voltage. For voltage-positioned circuits, connect FBS directly to FB near the IC to disable the FBS remote-sense integrator amplifier. To disable all three integrator amplifiers, connect FBS to VCC. Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typ) capacitor from CC to GND to set the integration time constant. CC can be left open if FBS is tied to VCC. Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 20 resistor. Bypass to GND with a 0.22F (min) capacitor.
2
SKP/SDN
3
TIME
4
FB
5
FBS
6 7 10
CC VCC
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
Pin Description (continued)
PIN NAME FUNCTION On-Time Selection Control Input. This is a four-level input that sets the K factor (Table 3) to determine DH on-time. Connect TON to the following pins for the indicated operation: GND = 1000kHz REF = 550kHz Open = 300kHz VCC = 200kHz 2.0V Reference Output. Bypass to GND with 0.22F (min) capacitor. Can source 50A for external loads. Loading REF degrades FB accuracy according to the REF load-regulation error. Current-Limit Adjustment. The GND - LX current-limit threshold defaults to 100mV if ILIM is tied to VCC. In adjustable mode, the current-limit threshold voltage is 1/10th the voltage seen at ILIM over a 0.5V to 3.0V range. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. Tie ILIM to REF for a fixed 200mV threshold. Ground Remote-Sense Input. For nonvoltage-positioned circuits, connect GNDS to ground directly at the load. GNDS internally connects to the integrator that fine tunes the output voltage. The output voltage rises by an amount of GNDS - GND. For voltage-positioned circuits, increase the output voltage (24mV typ) by biasing GNDS with a resistor-divider from REF to GND. Open-Drain Power-Good Output. VGATE is normally high when the output is in regulation. VGATE goes low whenever the DAC code changes, and returns high one clock period after the slew-rate controller finishes and the output is in regulation. VGATE is low in shutdown. Analog and Power Ground. Also connects to the current-limit comparator. Low-Side Gate Driver Output. DL swings GND to VDD. Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V. Bypass to GND with a 1F capacitor. Internal MUX Select Input. When A/B is high, the DAC code is determined by logic-level voltages on D0-D4. On the falling edge of A/B (or during power-up with A/B low), the DAC code is determined by the resistor values at D0-D4. DAC Code Inputs. D0 is the LSB and D4 is the MSB for the internal 5-bit DAC (see Table 4). When A/B is high, D0-D4 function as high-input-impedance logic inputs. On the falling edge of A/B (or during power-up with A/B low), the series resistance on each input sets its logic state as follows: (series resistance 1k 5%) = logic low (series resistance 100k 5%) = logic high Boost Flying Capacitor Connection. Connect BST to the external boost diode and capacitor as shown in the Standard Application Circuit. An optional resistor in series with BST allows the DH pull-up current to be adjusted (Figure 5). Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. It also connects to the current-limit comparator and the skip-mode zero-crossing comparator. High-Side Gate-Driver Output. DH swings LX to BST.
MAX1717
8
TON
9
REF
10
ILIM
11
GNDS
12 13 14 15 16
VGATE GND DL VDD A/B
17-21
D4-D0
22
BST
23 24
LX DH
______________________________________________________________________________________
11
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
VBATT 7V TO 24V +5V BIAS SUPPLY C5 1F R1 20 C6 1F
C1 4 x 10F, 25V
7 VCC 1 ON/OFF CONTROL 2 R7 120k V+ SKP/SDN VDD
15 22 24
D2 CMPSH-3
BST DH
Q1 C7 0.1F
3 21 20 19
L1 1H C2 6 x 470F KEMET T510
TIME D0 D1 D2 D3 D4 TON REF CC FB FBS GNDS 4 5 11 +5V DL GND 14 13 MAX1717 LX 23
VOUT A/B = LOW = 1.60V A/B = HIGH = 1.35V
TO VCC
Q2
D1
100k
18 17 C4 8 1F 9 6 C3 470pF
HIGH/LOW
16
A/B ILIM VGATE 10 TO VCC 12
R2 100k POWER-GOOD INDICATOR Q1 = IRF7811 Q2 = 2 x IRF7805 D1 = INTL RECT 10MQ040N C1 = TAIYO YUDEN TMK432BJ106KM C2 = KEMET T510X477M006 L1 = SUMIDA CEP125
Figure 1. Standard Application Circuit
12
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Table 1. Component Selection for Standard Applications
COMPONENT Figure Number Input Range (VBATT) Output Current Frequency High-Side MOSFET Q1 Low-Side MOSFET Q2 300kHz, STANDARD 300kHz, VOLTAGE APPLICATION, POSITIONED, CIRCUIT 1 CIRCUIT 2 1 7V to 24V 14A 300kHz International Rectifier IRF7811 (2) International Rectifier IRF7805, IRF7811, or IRF7811A (4) 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM (6) 470F, 6.3V tantalum Kemet T510X477M006AS 1H Sumida CEP125-1R0MC or Panasonic ETQP6F1R1BFA -- 3 7V to 24V 14A 300kHz International Rectifier IRF7811 (2) International Rectifier IRF7805, IRF7811, or IRF7811A (4) 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM (5) 220F, 2.5V, 25m specialty polymer Panasonic EEFUE0E221R 1H Sumida CEP125-1R0MC or Panasonic ETQP6F1R1BFA 5m 1%, 1W Dale WSL-2512-R005F 24mV Float 550kHz, VOLTAGE POSITIONED, CIRCUIT 3 3 7V to 24V 14A 550kHz International Rectifier IRF7811 (2) International Rectifier IRF7805, IRF7811, or IRF7811A (4) 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM (4) 220F, 2.5V, 25m specialty polymer Panasonic EEFUE0E221R 0.47H Sumida CEP125-4712-T006 5m 1%, 1W Dale WSL-2512-R005F 24mV REF 1000kHz, +5V, CIRCUIT 4 3 4.5V to 5.5V 14A 1000kHz International Rectifier IRF7811 (2) International Rectifier IRF7805, IRF7811, or IRF7811A (5) 22F, 10V ceramic Taiyo Yuden LMK432BJ226KM (5) 47F, 6.3V ceramic Taiyo Yuden JMK432BJ476MM 1000kHz, VOLTAGE POSITIONED, CIRCUIT 5 3 7V to 24V 14A 1000kHz International Rectifier IRF7811 (2) International Rectifier IRF7805, IRF7811, or IRF7811A (4) 10F, 25V ceramic Taiyo Yuden TMK432BJ106KM (5) 47F, 6.3V ceramic Taiyo Yuden JMK432BJ476MM 0.3H Sumida CEP12D38 4713T001 5m 1%, 1W Dale WSL-2512-R005F 24mV GND
Input Capacitor C1
Output Capacitor C2
Inductor L1
0.19H Coilcraft X8357-A 5m 1%, 1W Dale WSL-2512-R005F 24mV GND
VoltagePositioning Resistor R6 VoltagePositioning Offset TON Level Float
--
______________________________________________________________________________________
13
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Table 2. Component Suppliers
MANUFACTURER Coilcraft Dale-Vishay International Rectifier Kemet Panasonic Sumida Taiyo Yuden USA PHONE 847-639-6400 402-564-3131 310-322-3331 408-986-0424 714-373-7939 847-956-0666 408-573-4150 FACTORY FAX [Country Code] [1] 847-639-1469 [1] 402-563-6418 [1] 310-322-3332 [1] 408-986-1442 [1] 714-373-7183 [81] 3-3607-5144 [1] 408-573-4159
one-shot sets a minimum off-time (400ns typ). The ontime one-shot is triggered if the error comparator is low, the low-side switch current is below the current-limit threshold, and the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. On-Time = K (VOUT + 0.075V) / VIN where K is set by the TON pin-strap connection and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch (Table 3). The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics table (10% at 200kHz and 300kHz, 12% at 550kHz and 1000kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wide range. For example, the 1000kHz setting will typically run about 10% slower with inputs much greater than +5V due to the very short ontimes required. On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the
Detailed Description
+5V Bias Supply (VCC and VDD) The MAX1717 requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V supply can be generated with an external linear regulator. The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is:
IBIAS = ICC + f (QG1 + QG2) = 10mA to 40mA (typ) where ICC is 700A (typ), f is the switching frequency, and QG1 and QG2 are the MOSFET data sheet total gate-charge specification limits at VGS = 5V. V+ and VDD can be tied together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SKP/SDN going from low to high or open) must be delayed until the battery voltage is present to ensure startup.
Free-Running, Constant On-Time PWM Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudofixedfrequency, constant-on-time current-mode type with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor's ESR to act as the currentsense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a oneshot whose period is inversely proportional to input voltage and directly proportional to output voltage. Another
14
Table 3. Approximate K-Factors Errors
TON K APPROXIMATE MIN RECOMMENDED SETTING FACTOR K-FACTOR VBATT AT VOUT = 1.6V (kHz) (s) ERROR (%) (V) 200 300 550 1000 5 3.3 1.8 1.0 10 10 12.5 12.5 2.1 2.3 3.2 4.5
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
VBATT 2V TO 28V REF
V+
ILIM
MAX1717
TOFF TON ON-TIME COMPUTE FROM D/A 1-SHOT TRIG Q +5V 9
1
BST
TON TRIG 1-SHOT Q
S R
Q CURRENT LIMIT DH LX OUTPUT +5V
SKP/SDN
ERROR AMP REF 70k 10k ZERO CROSSING VDD DL S Q R GND FB FB REF +12% OVP/UVP DETECT
CC gm GNDS FBS REF -7% gm gm
REF
CHIP SUPPLY
VCC
+5V
VGATE
R-2R D/A CONVERTER
2V REF
REF
MUX AND SLEW CONTROL A/B D0 D1 D2 D3 D4 TIME
120k
Figure 2. Functional Diagram
______________________________________________________________________________________
15
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. The dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only in PWM mode (SKP/SDN = open) and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: = (VOUT + VDROP1) / tON (VIN + VDROP1 - VDROP2) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tON is the on-time calculated by the MAX1717. they can interfere with achieving the fastest possible load-transient response. The fastest transient response is achieved when all three integrators are disabled. This can work very well if the MAX1717 circuit is placed very close to the CPU. All three integrators can be disabled by connecting FBS to VCC. When the integrators are disabled, CC can be left unconnected, which eliminates a component, but leaves GNDS connected to any convenient ground. When the inductor is in continuous conduction, the output voltage will have a DC regulation higher than the trip level by 50% of the ripple. In discontinuous conduction (SKP/SDN open, light-loaded), the output voltage will have a DC regulation higher than the trip level by approximately 1.5% due to slope compensation. There is often a connector, or at least many milliohms of PC board trace resistance, between the DC-DC converter and the CPU. In these cases, the best strategy is to place most of the bulk bypass capacitors close to the CPU, with just one capacitor on the other side of the connector near the MAX1717 to control ripple if the CPU card is unplugged. In this situation, the remotesense lines (GNDS and FBS) and integrators provide a real benefit. When operating the MAX1717 in a voltage-positioned circuit (Figure 3), GNDS can be offset with a resistor divider from REF to GND, which causes the GNDS integrator to increase the output voltage by 90% of the applied offset (27mV typ). A low-value (5m typ) voltagepositioning resistor is added in series between the external inductor and the output capacitor. FBS is connected to FB directly at the junction of the external inductor and the voltage-positioning resistor. The net effect of these two changes is an output voltage that is slightly higher than the programmed DAC voltage at light loads, and slightly less than the DAC voltage at full-load current. For further information on voltage-positioning, see the Applications section.
MAX1717
Integrator Amplifiers
Three integrator amplifiers provide a fine adjustment to the output regulation point. One amplifier integrates the difference between GNDS and GND, a second integrates the difference between FBS and FB. The third amplifier integrates the difference between REF and the DAC output. These three transconductance amplifiers' outputs are directly summed inside the chip, so the integration time constant can be set easily with one capacitor. The gm of each amplifier is 160mho (typ). The integrator block has the ability to lower the output voltage by 2% and raise it by 6%. For each amplifier, the differential input voltage range is at least 70mV total, including DC offset and AC ripple. The integrator corrects for approximately 90% of the total error, due to finite gain. The FBS amplifier corrects for DC voltage drops in PC board traces and connectors in the output bus path between the DC-DC converter and the load. The GNDS amplifier performs a similar DC correction task for the output ground bus. The third integrator amplifier corrects the small offset of the error amplifier and provides an averaging function that forces VOUT to be regulated at the average value of the output ripple waveform. Integrators have both beneficial and detrimental characteristics. Although they correct for drops due to DC bus resistance and tighten the DC output voltage tolerance limits by averaging the peak-to-peak output ripple,
16
Automatic Pulse-Skipping Switchover
In skip mode (SKP/SDN high), an inherent automatic switchover to PFM takes place at light loads (Figure 4). This switchover is effected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (see the Continuous-to-Discontinuous Inductor Current Point graph in the Typical Operating Characteristics). For a battery range of 7V to 24V, this threshold is relatively constant, with only a minor dependence on battery voltage:
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
VBATT +5V BIAS SUPPLY C5 1F R1 20 C6 1F C1 7 VCC 1 ON/OFF CONTROL 2 R7 120k V+ SKP/SDN VDD BST DH 22 24 C7 0.1F MAX1717 LX DL GND 23 14 13 15
D2 CMPSH-3
Q1
3 21 20 19
L1 1H
R6 0.005 C2
TIME D0 D1 D2 D3 D4 TON REF CC FB FBS GNDS 4 5 11 +5V
VOUT A/B = LOW = 1.60V A/B = HIGH = 1.35V
TO VCC
Q2
D1
100k
18 17 C4 8 1F 9 6 C3 470pF
R4 2k
HIGH/LOW
16
A/B ILIM VGATE 10 TO VCC 12
R2 100k POWER-GOOD INDICATOR
R5 150k TO VREF D1 = INTL RECT 10MQ040N. FOR OTHER COMPONENTS, SEE TABLE 1 VALUES.
Figure 3. Voltage-Positioned Circuit
I LOAD(SKIP)
K
VOUT 2L
VBATT - VOUT VBATT
where K is the on-time scale factor (Table 3). The loadcurrent level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). For example, in the standard application circuit this becomes: 3.3s 1.6V 2 1H
12V - 1.6V
12V
= 2.3A
The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels).
______________________________________________________________________________________
17
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
i t INDUCTOR CURRENT = VBATT - VOUT L -IPEAK -IPEAK ILOAD INDUCTOR CURRENT
ILOAD = IPEAK/2
ILIMIT
0
ON-TIME
TIME
0
TIME
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Figure 5. "Valley" Current-Limit Threshold Point
Forced-PWM Mode (SKP/SDN Open)
The low-noise forced-PWM mode (SKP/SDN open) disables the zero-crossing comparator that controls the low-side switch on-time. This causes the low-side gatedrive waveform to become the complement of the highside gate-drive waveform. This in turn causes the inductor current to reverse at light loads as the PWM loop strives to maintain a duty ratio of VOUT/VBATT. The benefit of forced-PWM mode is to keep the switching frequency fairly constant, but it comes at a cost: the noload battery current can be 10mA to 40mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is most useful for reducing audiofrequency noise and improving the cross-regulation of multiple-output applications that use a flyback transformer or coupled inductor.
Current-Limit Circuit
The current-limit circuit employs a unique "valley" currentsensing algorithm that uses the on-resistance of the low-side MOSFET as a current-sensing element. If the current-sense signal is above the current-limit threshold, the PWM is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the MOSFET on-resistance, inductor value, and battery voltage. The reward for this uncertainty is robust, lossless overcurrent sensing. When combined with the undervoltage protection circuit, this currentlimit method is effective in almost every circumstance. There is also a negative current limit that prevents excessive reverse inductor currents when VOUT is sinking
18
current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. The current-limit threshold adjustment range is from 50mV to 300mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 100mV when ILIM is connected to VCC. The logic threshold for switchover to the 100mV default value is approximately VCC - 1V. The adjustable current limit accommodates MOSFETs with a wide range of on-resistance characteristics (see Design Procedure). Carefully observe the PC board layout guidelines to ensure that noise and DC errors don't corrupt the currentsense signals seen by LX and GND. Place the IC close to the low-side MOSFET with short, direct traces, making a Kelvin sense connection to the source and drain terminals.
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in the notebook CPU environment, where a large VBATT - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the MAX1717 will interpret the MOSFET gate as "off" while
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
there is actually still charge left on the gate. Use very short, wide traces measuring 10 to 20 squares (50 to 100 mils wide if the MOSFET is 1 inch from the MAX1717). The dead time at the other edge (DH turning off) is determined by a fixed 35ns (typ) internal delay. The internal pull-down transistor that drives DL low is robust, with a 0.5 typical on-resistance. This helps prevent DL from being pulled up during the fast risetime of the inductor node, due to capacitive coupling from the drain to the gate of the low-side synchronousrectifier MOSFET. However, for high-current applications, you might still encounter some combinations of highand low-side FETs that will cause excessive gate-drain coupling, which can lead to efficiency-killing, EMIproducing shoot-through currents. This is often remedied by adding a resistor in series with BST, which increases the turn-on time of the high-side FET without degrading the turn-off time (Figure 6).
Shutdown
When SKP/SDN goes low, the MAX1717 goes into lowpower shutdown mode. VGATE goes low immediately. The output voltage ramps down to 0 in 25mV steps at the clock rate set by RTIME. When the DAC reaches the 0V setting, DL goes high, DH goes low, the reference is turned off, and the supply current drops to about 2A. When SKP/SDN goes high or floats, the reference powers up, and after the reference UVLO is passed, the DAC target is evaluated and switching begins. The slew-rate controller ramps up from zero in 25mV steps to the currently selected code value (based on A/B). There is no traditional soft-start (variable current limit) circuitry, so full output current is available immediately. VGATE goes high after the slew-rate controller has terminated and the output voltage is in regulation. As soon as VGATE goes high, full power is available.
MAX1717
UVLO
If the VCC voltage drops low enough to trip the UVLO comparator, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, DL is forced high in this mode. This will force the output to GND, but it will not use the slew-rate controller. This results in large negative inductor current and possibly small negative output voltages. If VCC is likely to drop in this fashion, the output can be clamped with a Schottky diode to GND to reduce the negative excursion.
POR
Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the PWM for operation. V CC undervoltage lockout (UVLO) circuitry inhibits switching, forces VGATE low, and forces the DL gate driver high (to enforce output overvoltage protection). When VCC rises above 4.2V, the DAC inputs are sampled and the output voltage begins to slew to the DAC setting. For automatic startup, the battery voltage should be present before VCC. If the MAX1717 attempts to bring the output into regulation without the battery voltage present, the fault latch will trip. The SKP/SDN pin can be toggled to reset the fault latch.
DAC Inputs D0-D4
The digital-to-analog converter (DAC) programs the output voltage. It typically receives a preset digital code from the CPU pins, which are either hard-wired to GND or left open-circuit. They can also be driven by digital logic, general-purpose I/O, or an external mux. Do not leave D0-D4 floating--use 1M or less pull-ups if the inputs may float. D0-D4 can be changed while the SMPS is active, initiating a transition to a new output voltage level. If this mode of DAC control is used, connect A/B high. Change D0-D4 together, avoiding greater than 1s skew between bits. Otherwise, incorrect DAC readings may cause a partial transition to the wrong voltage level, followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages (Table 4) are compatible with Intel's mobile Pentium(R) III specification.
+5V VBATT BST 5 TYP
DH LX
MAX1717
A/B Internal Mux
The MAX1717 contains an internal mux that can be used to select one of two programmed DAC codes and output
Figure 6. Reducing the Switching-Node Rise Time
Pentium is a registered trademark of Intel Corp. 19
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
voltages. The internal mux is controlled with the A/B pin, which selects between the A mode and the B mode. In the A mode, the voltage levels on D0-D4 select the output voltage according to Table 4. Do not leave D0-D4 floating; there are no internal pull-up resistors. The B mode is programmed by external resistors in series with D0-D4, using a unique scheme that allows two sets of data bits using only one set of pins (Figure 7). When A/B goes low (or during power-up with A/B low), D0-D4 are tested to see if there is a large resistance in series with the pin. If the voltage level on the pin is a logic low, an internal switch connects the pin to an internal 40k pull-up for about 4s to see if the pin voltage can be forced high (Figure 8). If the pin voltage cannot be pulled to a logic high, the pin is considered low impedance and its B-mode logic state is low. If the pin can be pulled to a logic high, the impedance is considered high and so is the B-mode logic state. Similarly, if the voltage level on the pin is a logic high, an internal switch connects the pin to an internal 8k pull-down to see if the pin voltage can be forced low. If so, the pin is high-impedance and its B-mode logic state is high. Otherwise, its logic state is low. A high pin impedance (and logic high) is 100k or greater, and a low impedance (and logic low) is 1k or less. The Electrical Characteristics table guaranteed levels for these impedances are 95k and 1.05k to allow the use of standard 100k and 1k resistors with 5% tolerance. If the output voltage codes are fixed at PC board design time, program both codes with a simple combination of pin-strap connections and series resistors (Figure 7). If the output voltage codes are chosen during PC board assembly, both codes can be independently programmed with resistors (Figure 9). This matrix of 10 resistor-footprints can be programmed to all possible A-mode and B-mode code combinations with only five resistors. Often, one or more output-voltage codes are provided directly by the CPU's VID pins. If the CPU actively drives these pins, connect A/B high (A mode) and let the CPU determine the output voltages. If the B mode is needed for startup or other reasons, insert resistors in series with D0-D4 to program the B-mode voltage. Be sure that the VID pins are actively driven at all times. If the CPU's VID pins float, the open-circuit pins can present a problem for the MAX1717's internal mux. The processor's VID pins can be used for the A-mode setting, together with suitable pull-up resistors. However, the B-mode VID code is set with resistors in series with D0-D4, and in order for the B-mode to work, any pins
20
MAX1717
Table 4. Output Voltage vs. DAC Codes
D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 No CPU 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 No CPU
Note: In the no-CPU state, DH and DL are held low and the slew-rate controller is set for 0.9V.
intended to be B-mode logic low must appear to be low impedance, at least for the 4s sampling interval. This can be achieved in several ways, including the following two (Figure 10). By using low-impedance pull-up resistors with the CPU's VID pins, each pin provides the low impedance needed for the mux to correctly interpret the B-mode setting. Unfortunately, the low resistances cause several mA additional quiescent current
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
for each of the CPU's grounded VID pins. This quiescent current can be avoided by taking advantage of the fact that D0-D4 need only appear low impedance briefly, not necessarily on a continuous DC basis. Highimpedance pull-ups can also be used if they are bypassed with a large enough capacitance to make them appear low impedance for the 4s sampling interval. As noted in Figure 10, 4.7nF capacitors allow the inputs to appear low impedance even though they are pulled up with 1M resistors.
MAX1717
3.0V TO 5.5V
MAX1717
D4 100k D3 A-MODE VID = 01101 1.35V D2 D1 D0 A/B B-MODE VID = 01000 1.60V A/B = LOW = 1.60V A/B = HIGH = 1.35V
Output Voltage Transition Timing
The MAX1717 is designed to perform output voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. This makes the IC very suitable for CPUs featuring SpeedStep technology and
Figure 7. Using the Internal Mux with Hard-Wired A-Mode and B-Mode DAC Codes
+5V VCC
MAX1717
3.0V TO 5.5V 40k 40k 40k 40k 40k
D4 100k D3 D2 D1 D0 B-DATA LATCH
8k
8k
8k
8k
8k
GND
Figure 8. Internal Mux B-Mode Data Test and Latch ______________________________________________________________________________________ 21
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
2.7V TO 5.5V
1k
1k
100k
MAX1717
D4 D3 D2 D1 D0 A/B 1k 1k A/B = LOW = 1.60V A/B = HIGH = 1.35V
NOTE: USE PULL-UP FOR A-MODE 1, PULL-DOWN FOR A-MODE 0. USE 100k FOR B-MODE 1, 1k FOR B-MODE 0.
Figure 9. Using the Internal Mux with Both VID Codes Resistor Programmed
other ICs that operate in two or more modes with different core voltage levels. Intel's mobile Pentium III CPU with SpeedStep technology operates at two distinct clock frequencies and requires two distinct core voltages. When transitioning from one clock frequency to the other, the CPU first goes into a low-power state, then the output voltage and clock frequency are changed. The change must be accomplished in 100s or the system may halt. At the beginning of an output voltage transition, the MAX1717 brings the VGATE output low, indicating that a transition is beginning. VGATE remains low during the transition and goes high when the slew-rate controller has set the internal DAC to the final value and one additional slew-rate clock period has passed. The slewrate clock frequency (set by resistor RTIME) must be set fast enough to ensure that VGATE goes high within the allowed 100s. Alternatively, the slew-rate clock can be set faster than necessary and VGATE's rising edge can be detected so that normal system operation can resume even earlier. The output voltage transition is performed in 25mV steps, preceded by a 4s delay and followed by one
22
additional clock period after which VGATE goes high if the output voltage is in regulation. The total time for a transition depends on RTIME, the voltage difference, and the accuracy of the MAX1717's slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1717 will automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less than the current limit set by ILIM. The transition time is given by: 1V OLD - VNEW 4s + 1 + SLEW 25mV where SLEW = 150kHz * 120k / RTIME, VOLD is the original output voltage, and VNEW is the new output voltage. See Time Frequency Accuracy in Electrical Characteristics for SLEW accuracy. The practical range of RTIME is 47k to 470k, corresponding to 2.6s to 26s per 25mV step. Although the DAC takes discrete 25mV steps, the output filter makes
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
3.15 TO 5.5V *OPTIONAL
4.7nF
1M
1k
1k
1k
1k
1k
MAX1717
D4 100k D3 CPU D2 D1 D0 A/B CPU VID = 01101 1.35V (A-MODE) B-MODE VID = 01000 1.6V A/B = LOW = 1.60V A/B = HIGH = 1.35V
*TO REDUCE QUIESCENT CURRENT, 1k PULL-UP RESISTORS CAN BE REPLACED BY 1M RESISTORS WITH 4.7nF CAPACATORS IN PARALLEL.
Figure 10. Using the Internal Mux with CPU Driving the A-Mode VID Code
the transitions relatively smooth. The average inductor current required to make an output voltage transition is: IL COUT * 25mV * SLEW
Overvoltage protection can be defeated through the NO FAULT test mode (see the NO FAULT Test Mode section).
Output Overvoltage Protection
The overvoltage protection (OVP) circuit is designed to protect against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The output voltage is continuously monitored for overvoltage. If the output is more than 2.25V, OVP is triggered and the circuit shuts down. The DL low-side gate-driver output is then latched high until SKP/SDN is toggled or VCC power is cycled below 1V. This action turns on the synchronous-rectifier MOSFET with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse will blow. DL is also kept high continuously when VCC UVLO is active, as well as in shutdown mode (Table 5).
Output Undervoltage Shutdown
The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1717 output voltage is under 70% of the nominal value, the PWM is latched off and won't restart until VCC power is cycled or SKP/SDN is toggled. To allow startup, UVP is ignored during the undervoltage fault-blanking time (the first 256 cycles of the slew rate after startup). UVP can be defeated through the NO FAULT test mode (see the NO FAULT Test Mode section).
NO FAULT Test Mode
The over/undervoltage protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a test mode is provided to disable totally the OVP, UVP, and thermal shutdown features, and clear the fault latch if it has
23
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Table 5. Operating Mode Truth Table
SKP/SDN GND DL High MODE Shutdown COMMENT Low-power shutdown state. DL is forced to VDD, enforcing OVP. ICC + IDD = 2A typ. Test mode with faults disabled and fault latches cleared, including thermal shutdown. Otherwise, normal operation, with automatic PWM/PFM switchover for pulse-skipping at light loads. Low-noise operation with no automatic switchover. Fixed-frequency PWM action is forced regardless of load. Inductor current reverses at light load levels. Normal operation with automatic PWM/PFM switchover for pulse-skipping at light loads. Fault latch has been set by OVP, UVP, or thermal shutdown. Device will remain in FAULT mode until VCC power is cycled or SKP/SDN is forced low.
12V to 15V
Switching
No Fault
Float
Switching
Run (PWM, low noise) Run (PFM/PWM, normal operation) Fault
VCC
Switching
VCC or Float
High
been set. The PWM operates as if SKP/SDN were high (SKIP mode). The NO FAULT test mode is entered by forcing 12V to 15V on SKP/SDN.
Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: 1) Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. 2) Maximum Load Current. There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) * 80%. 3) Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. 4) Inductor Operating Point. This choice provides tradeoffs between size vs. efficiency. Low inductor values cause large ripple currents, resulting in the smallest size, but poor efficiency and high output noise. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The MAX1717's pulse-skipping algorithm initiates skip mode at the critical conduction point. So, the inductor operating point also determines the loadcurrent value at which PFM/PWM switchover occurs. The optimum point is usually found between 20% and 50% ripple current. 5) The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time:
24
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
V (ILOAD1 - ILOAD2 )2 L K OUT + t OFF(MIN) VIN VSAG = V - VOUT 2 COUT VOUT K IN - t OFF(MIN) VIN where tOFF(MIN) is the minimum off-time (see Electrical Characteristics) and K is from Table 3. Examining the Figure 1 example with a Q2 maximum RDS(ON) = 5.5m at TJ = +25C and 7.5m at TJ = +100C reveals the following: ILIMIT(LOW) = 90mV / 7.5m = 11.9A and the required valley current limit is: ILIMIT(LOW) > 14A - (0.3012) 14A = 11.9A Therefore, the circuit can deliver the full-rated 14A using the default ILIM threshold. When delivering 14A of output current, the worst-case power dissipation of Q2 is 1.48W. With a thermal resistance of 60C/W and each MOSFET dissipating 0.74W, the temperature rise of the MOSFETs is 60C/W * 0.74W = 44.5C, and the maximum ambient temperature is +100C - 44.5C = +55.5C. To operate at a higher ambient temperature, choose lower RDS(ON) MOSFETs or reduce the thermal resistance. You could also raise the current-limit threshold, allowing operation with a higher MOSFET junction temperature. Connect ILIM to VCC for a default 100mV current-limit threshold. For an adjustable threshold, connect a resistor divider from REF to GND, with ILIM connected to the center tap. The external adjustment range of 0.5V to 3.0V corresponds to a current-limit threshold of 50mV to 300mV. When adjusting the current limit, use 1% tolerance resistors and a 10A divider current to prevent a significant increase of errors in the current-limit tolerance.
MAX1717
Inductor Selection
The switching frequency and operating point (% ripple or LIR) determine the inductor value as follows: L= VOUT VIN - VOUT
VIN
SW LIR ILOAD(MAX)
(
)
Example: ILOAD(MAX) = 14A, VIN = 7V, VOUT = 1.6V, SW = 300kHz, 30% ripple current or LIR = 0.30. 1.6V (7V - 1.6V) = 0.98H 7V 300kHz 0.30 14A
L=
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK). IPEAK = ILOAD(MAX) + (LIR / 2) ILOAD(MAX)
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and loadtransient requirements, yet have high enough ESR to satisfy stability requirements. Also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to no-load condition without tripping the OVP circuit. In CPU VCORE converters and other applications where the output is subject to violent load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR VSTEP / ILOAD(MAX) The actual microfarad capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and volt-
Setting the Current Limit
The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half of the ripple current; therefore: ILIMIT(LOW) > ILOAD(MAX) - (LIR / 2) ILOAD(MAX) where I LIMIT(LOW) equals the minimum current-limit threshold voltage divided by the RDS(ON) of Q2. For the MAX1717, the minimum current-limit threshold (100mV default setting) is 90mV. Use the worst-case maximum value for RDS(ON) from the MOSFET Q2 data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each C of temperature rise.
______________________________________________________________________________________
25
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
age rating rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics). When using low-capacity filter capacitors such as ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and VSOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG equation in the Design Procedure). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR L IPEAK 2 2 C VOUT unstable operation. However, it's easy to add enough series resistance by placing the capacitors a couple of inches downstream from the junction of the inductor and FB pin, or use a voltage-positioned circuit (see Voltage Positioning and Effective Efficiency section). Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there isn't enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Doublepulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability, which is caused by insufficient ESR. Loop instability can result in oscillations at the output after line or load perturbations that can cause the output voltage to rise above or fall below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Don't allow more than one cycle of ringing after the initial step-response under/overshoot.
MAX1717
where IPEAK is the peak inductor current.
Output Capacitor Stability Considerations
Stability is determined by the value of the ESR zero relative to the switching frequency. The voltage-positioned circuits in this data sheet have their ESR zero frequencies lowered due to the external resistor in series with the output capacitor ESR, guaranteeing stability. For voltagepositioned circuits, the minimum ESR requirement of the output capacitor is reduced by the voltage-positioning resistor value. For nonvoltage-positioned circuits, the following criteria must be satisfied. The boundary of instability is given by the following equation: ESR SW / where : ESR = 1 2
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD VOUT VIN - VOUT VIN
RESR
(
)
COUT
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 15kHz. In the standard application used for inductor selection, the ESR needed to support 50mVp-p ripple is 50mV/4.2A = 11.9m. Six 470F/4V Kemet T510 low-ESR tantalum capacitors in parallel provide 5m max ESR. Their typical combined ESR results in a zero at 17kHz, well within the bounds of stability. Don't put high-value ceramic capacitors directly across the fast-feedback inputs (FB to GND) without taking precautions to ensure stability. Ceramic capacitors have a high ESR zero frequency and may cause erratic,
26
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or a connector in series with the battery. If the MAX1717 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability (>12A) when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
For maximum efficiency, choose a high-side MOSFET (Q1) that has conduction losses equal to the switching losses at the optimum battery voltage (15V). Check to ensure that the conduction losses at minimum input voltage don't exceed the package thermal limits or violate the overall thermal budget. Check to ensure that conduction losses plus switching losses at the maximum input voltage don't exceed the package ratings or violate the overall thermal budget. Choose a low-side MOSFET (Q2) that has the lowest possible RDS(ON), comes in a moderate-sized package (i.e., one or two SO-8s, DPAK or D2PAK), and is reasonably priced. Ensure that the MAX1717 DL gate driver can drive Q2; in other words, check that the dv/dt caused by Q1 turning on does not pull up the Q2 gate due to drain-to-gate capacitance, causing cross-conduction problems. Switching losses aren't an issue for the low-side MOSFET since it's a zero-voltage switched device when used in the buck topology. tion, preferably including verification using a thermocouple mounted on Q1: PD(Q1 Switching) = CRSS VIN(MAX)
2
MAX1717
SW I LOAD
IGATE
where CRSS is the reverse transfer capacitance of Q1 and IGATE is the peak gate-drive source/sink current (1A typ). For the low-side MOSFET (Q2), the worst-case power dissipation always occurs at maximum battery voltage: VOUT 2 PD(Q2) = 1 - ILOAD RDS(ON) VIN(MAX) The absolute worst case for MOSFET power dissipation occurs under heavy overloads that are greater than ILOAD(MAX) but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "overdesign" the circuit to tolerate: ILOAD = ILIMIT(HIGH) + (LIR / 2) * ILOAD(MAX) where I LIMIT(HIGH) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. This means that the MOSFETs must be very well heatsinked. If short-circuit protection without overload protection is enough, a normal ILOAD value can be used for calculating component stresses. Choose a Schottky diode (D1) having a forward voltage low enough to prevent the Q2 MOSFET body diode from turning on during the dead time. As a general rule, a diode having a DC current rating equal to 1/3 of the load current is sufficient. This diode is optional and can be removed if efficiency isn't critical.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation due to resistance occurs at minimum battery voltage: V PD (Q1 Re sistive) = OUT ILOAD2 RDS(ON) VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. High-side switching losses don't usually become an issue until the input is greater than approximately 15V. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2SW switching-loss equation. If the high-side MOSFET you've chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VIN(MAX), reconsider your choice of MOSFET. Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evalua-
Application Issues
Voltage Positioning and Effective Efficiency
Powering new mobile processors requires new techniques to reduce cost, size, and power dissipation. Voltage positioning reduces the total number of output capacitors to meet a given transient response requirement. Setting the no-load output voltage slightly higher allows a larger step down when the output current suddenly increases, and regulating at the lower output voltage under load allows a larger step up when the output current suddenly decreases. Allowing a larger step size means that the output capacitance can be reduced and the capacitor's ESR can be increased.
27
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
The no-load output voltage is raised by adding a fixed offset to GNDS through a resistor divider from REF. A 27mV nominal value is appropriate for 1.6V applications. This 27mV corresponds to a 0.9 * 27mV = 24mV = 1.5% increase with a VOUT of 1.6V. In the voltage-positioned circuit (Figure 3), this is realized with resistors R4 and R5. Use a 10A resistor divider current. Adding a series output resistor positions the full-load output voltage below the actual DAC programmed voltage. Connect FB and FBS directly to the inductor side of the voltage-positioning resistor (R6, 5m). The other side of the voltage-positioning resistor should be tied directly to the output filter capacitor with a short, wide PC board trace. With a 14A full-load current, R6 causes a 70mV drop. This 70mV is a -4.4% error, but it is compensated by the +1.5% error from the GNDS offset, resulting in a net error of -2.9%. This is well within the typical specification for voltage accuracy. An additional benefit of voltage positioning is reduced power consumption at high load currents. Because the output voltage is lower under load, the CPU draws less current. The result is lower power dissipation in the CPU, though some extra power is dissipated in R6. For a nominal 1.6V, 12A output, reducing the output voltage 2.9% gives an output voltage of 1.55V and an output current of 11.65A. Given these values, CPU power consumption is reduced from 19.2W to 18.1W. The additional power consumption of R6 is: 5m * 11.65A2 = 0.68W and the overall power savings is as follows: 19.2 - (18.1 + 0.68) = 0.42W
DH VBATT
where VNP = 1.6V (in this example). 4) Calculate effective efficiency as: Effective efficiency = (V NP * I NP ) / (V IN * I IN ) = calculated nonpositioned power output divided by the measured voltage-positioned power input. 5) Plot the efficiency data point at the nonpositioned current, INP. The effective efficiency of voltage-positioned circuits is shown in the Typical Operating Characteristics section.
Dropout Performance
The output voltage adjust range for continuous-conduction operation is restricted by the nonadjustable 500ns (max) minimum off-time one-shot (375ns max at 1000kHz). For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient response performance of buck regulators operated close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (IDOWN)
In effect, 1W of CPU dissipation is saved and the power supply dissipates much of the savings, but both the net savings and the transfer of dissipation away from the hot CPU are beneficial. Effective efficiency is defined as the efficiency required of a nonvoltage-positioned circuit to equal the total dissipation of a voltage-positioned circuit for a given CPU operating condition. Calculate effective efficiency as follows: 1) Start with the efficiency data for the positioned circuit (VIN, IIN, VOUT, IOUT). 2) Model the load resistance for each data point: RLOAD = VOUT / IOUT 3) Calculate the output current that would exist for each RLOAD data point in a nonpositioned application: INP = VNP / RLOAD
28
MAX1717 DL R1 FB 180k FBS GND R2 1k GNDS R2
VOUT
VOUT = VFB * 1 +
(
R1 R2 || 180k
)
Figure 11. Adjusting VOUT with a Resistor-Divider
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs
as much as it ramps up during the on-time (IUP). The ratio h = IUP/IDOWN is an indicator of ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current will be less able to increase during each switching cycle and VSAG will greatly increase unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but this may be adjusted up or down to allow tradeoffs between V SAG , output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: VIN(MIN) =
Adjusting VOUT with a Resistor-Divider The output voltage can be adjusted with a resistordivider rather than the DAC if desired (Figure 11). The drawback is that the on-time doesn't automatically receive correct compensation for changing output voltage levels. This can result in variable switching frequency as the resistor ratio is changed, and/or excessive switching frequency. The equation for adjusting the output voltage is: R1 VOUT = VFB 1 + R2 RINT
where VFB is the currently selected DAC value, and RINT is the FB input resistance. When using external resistors, FBS remote sensing is not recommended, but GNDS remote sensing is still possible. Connect FBS to FB, and GNDS to a remote ground location. In resistoradjusted circuits, the DAC code should be set as close as possible to the actual output voltage in order to minimize the shift in switching frequency.
MAX1717
T OFF(MIN ) x h 1- K
(
VOUT + VDROP1
)
+ VDROP2 - VDROP1
where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see On-Time One-Shot), TOFF(MIN) is from the Electrical Characteristics table, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example: VOUT = 1.6V fsw = 550kHz K = 1.8s, worst-case K = 1.58s TOFF(MIN) = 500ns VDROP1 = VDROP2 = 100mV h = 1.5 VIN(MIN) = (1.6V + 0.1V) / (1-0.5s * 1.5/1.58s) + 0.1V - 0.1V = 3.2V Calculating again with h = 1 gives the absolute limit of dropout: VIN(MIN) = (1.6V + 0.1V) / (1-1.0 0.5s/1.58s) - 0.1V + 0.1V = 2.5V Therefore, VIN must be greater than 2.5V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.2V.
Adjusting VOUT Above 2V The feed-forward circuit that makes the on-time dependent on battery voltage maintains a nearly constant switching frequency as VIN, ILOAD, and the DAC code are changed. This works extremely well as long as FB is connected directly to the output. When the output is adjusted with a resistor divider, the switching frequency is increased by the inverse of the divider ratio.
This change in frequency can be compensated with the addition of a resistor-divider to the battery-sense input (V+). Attach a resistor-divider from the battery voltage to V+ on the MAX1717, with the same attenuation factor as the output divider. The V+ input has a nominal input impedance of 600k, which should be considered when selecting resistor values.
One-Stage (Battery Input) vs. Two-Stage (5V Input) Applications
The MAX1717 can be used with a direct battery connection (one stage) or can obtain power from a regulated 5V supply (two stage). Each approach has advantages, and careful consideration should go into the selection of the final design. The one-stage approach offers smaller total inductor size and fewer capacitors overall due to the reduced demands on the 5V supply. The transient response of the single stage is better due to the ability to ramp the inductor current faster. The total efficiency of a single stage is better than the two-stage approach.
______________________________________________________________________________________
29
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
The two-stage approach allows flexible placement due to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the CPU for better regulation and lower I2R losses from PC board traces. Although the two-stage design has worse transient response than the single stage, this can be offset by the use of a voltage-positioned converter. switching power stage requires particular attention (Figure 12). If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout: 1) Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitterfree operation. 2) All analog grounding is done to a separate solid copper plane, which connects to the MAX1717 at the GND pin. This includes the V CC , REF, and CC capacitors, the TIME resistor, as well as any other resistor-dividers. 3) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. 4) LX and GND connections to Q2 for current limiting must be made using Kelvin sense connections to guarantee the current-limit accuracy. With SO-8 MOSFETs, this is best done by routing power to the MOSFETs from outside using the top copper layer, while connecting GND and LX inside (underneath) the SO-8 package. 5) When trade-offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharge path. For example, it's better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor. 6) Ensure the FB connection to the output is short and direct. In voltage-positioned circuits, the FB connection is at the junction of the inductor and the positioning resistor. 7) Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM). Make all pin-strap control input connections (SKP/SDN, ILIM, etc.) to analog ground or VCC rather than power ground or VDD.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are also expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability in nonvoltage-positioned circuits). In addition, their relatively low capacitance value can cause output overshoot when going abruptly from full-load to no-load conditions, unless the inductor value can be made small (high switching frequency), or there are some bulk tantalum or electrolytic capacitors in parallel to absorb the stored energy in the inductor. In some cases, there may be no room for electrolytics, creating a need for a DC-DC design that uses nothing but ceramics. The MAX1717 can take full advantage of the small size and low ESR of ceramic output capacitors in a voltagepositioned circuit. The addition of the positioning resistor increases the ripple at FB, lowering the effective ESR zero frequency of the ceramic output capacitor. Output overshoot (V SOAR) determines the minimum output capacitance requirement (see Output Capacitor Selection). Often the switching frequency is increased to 550kHz or 1000kHz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 2% to 3% and about 5% at 1000kHz when compared to the 300kHz voltagepositioned circuit, primarily due to the high-side MOSFET switching losses. Table 1 and the Typical Operating Characteristics include two circuits using ceramic capacitors with 1000kHz switching frequencies. The efficiency of the +5V input circuit (circuit 4) is substantially higher than circuit 5, which accommodates the full battery voltage range. Circuit 4 is an excellent choice for two-stage conversion applications if the goal is to minimize size and power dissipation near the CPU.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (Q2 source, CIN-, COUT-, D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The
30
______________________________________________________________________________________
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
VBATT GND IN
ALL ANALOG GROUNDS CONNECT TO LOCAL PLANE ONLY VIA TO GND NEAR Q2 SOURCE MAX1717 VCC CC REF
CIN Q1 VDD D1 Q2 COUT GND OUT
; ;
VOUT GND VIA TO SOURCE OF Q2 R6 L1 VIA TO FB AND FBS
CONNECT LOCAL ANALOG GROUND PLANE DIRECTLY TO GND FROM THE SIDE OPPOSITE THE VDD CAPACITOR GND TO AVOID VDD GROUND CURRENTS FROM FLOWING IN THE ANALOG GROUND PLANE. VIA TO LX
NOTES: "STAR" GROUND IS USED. D1 IS DIRECTLY ACROSS Q2.
INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE
Figure 12. Power-Stage PC Board Layout Example
2) Mount the controller IC adjacent to MOSFET Q2, preferably on the back side opposite Q2 in order to keep LX-GND current-sense lines and the DL drive line short and wide. The DL gate trace must be short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the MOSFET is 1 inch from the controller IC). 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figure 12. This diagram can be viewed as having three separate ground planes: output ground, where all the high-power components go; the GND plane, where the GND pin and VDD bypass capacitors
go; and an analog ground plane where sensitive analog components go. The analog ground plane and GND plane must meet only at a single point directly beneath the IC. These two planes are then connected to the high-power output ground with a short connection from GND to the source of the lowside MOSFET Q2 (the middle of the star ground). This point must also be very close to the output capacitor ground terminal. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.
______________________________________________________________________________________
31
Dynamically Adjustable, Synchronous Step-Down Controller for Notebook CPUs MAX1717
Pin Configuration
TOP VIEW
V+ 1 SKP/SDN 2 TIME 3 FB 4 FBS 5 CC 6 VCC 7 TON 8 REF 9 ILIM 10 GNDS 11 VGATE 12 24 DH 23 LX 22 BST 21 D0
Chip Information
TRANSISTOR COUNT: 7151
MAX1717
20 D1 19 D2 18 D3 17 D4 16 A/B 15 VDD 14 DL 13 GND
QSOP
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX1717

	To Download MAX1717 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .